1. Field of the Invention
The invention relates to an ESD protective transistor and in particular to an ESD protective transistor for protecting integrated circuits (ICs) against electrostatic discharge (ESD).
2. Description of Prior Art
For mixed processes, there are available protective elements with different breakdown voltages determined by technological parameters, which are designed for the corresponding supply voltages. Such supply voltages may be, for example, 6V, 12V or 20V. If a higher supply voltage is necessary for an application, these elements cannot be used any more.
In case of such applications it is possible, for example, to make use of MOS transistors the drain electrode and gate electrode of which are actively clamped by means of Zener diodes. However, such known ESD protection devices require very much space and thus involve high costs.
Another known ESD protection device is described, for example, in DE 19746410 A1 which teaches the use of a vertical bipolar transistor the breakdown voltage of which can be matched to the demanded supply voltage by a suitable layout measure. Such a vertical transistor is shown in FIG. 5, in which a heavily doped p+ base region 2 and a heavily doped n+ emitter region 4 are arranged in a lightly doped p-well 6 formed in a semiconductor substrate 8. Furthermore, there is provided a buried, heavily doped n+ collector layer 10 that is separated from p-well 6 by a lightly doped n-type region 12. The buried n+ collector layer 10 is connected via a vertical n+ diffusion 14 to a heavily doped n+ region 16 in the surface of substrate 8. The heavily doped n+ region 16 is provided with a collector electrode 18, whereas the base region 2 and the emitter region 4 are short-circuited via a base-emitter electrode 20. According to said DE 19746410 A1, the distance a between the heavily doped n+ region 16 and the lightly doped p-well is adjusted such that an avalanche breakdown voltage between these regions is determined by the lateral distance a, and not by the procedurally necessitated vertical distance between buried layer 10 and p-well 6. The base region 2 and the emitter region 4 are shorted so that, after onset of the avalanche breakdown on the collector side, the p-well 6 is charged so that the vertical transistor can trigger. In this manner, very low-impedance behavior is obtained.
The disadvantage of the structure shown in FIG. 5 is the fixed holding voltage defined by the non-variable base width and base doping of the vertical transistor. In case of the element illustrated in FIG. 5, this is due to the fact that the base region 2 and the emitter region 4 are shorted so that, after breakdown of the space charge region on the collector side, the transistor effect commences and the element snaps back to its specific holding voltage determined by the base width.
To safely exclude permanent switching on of the protective transistor during regular operation, however, it is necessary to have a holding voltage that is above the supply voltage of the integrated circuit.
U.S. Pat. No. 5,268,588 discloses a semiconductor structure for protection against electrostatic discharge, comprising two bipolar transistors and one field effect transistor. The emitter of the first bipolar transistor is connected to the collectors of the first and second bipolar transistors, whereas the emitter of the second bipolar transistor is connected to a reference voltage potential.
EP 0 822 596 A discloses a semiconductor circuit with ESD protection, with an ESD protection circuit being formed by an npnp semiconductor structure representing an npn transistor and a pnp transistor connected thereto, with the emitter of the npn transistor being connected to a first potential and the emitter of the pnp transistor being connected to a substrate potential.
The document WO 94/03928 A is concerned with a semiconductor high-voltage protection circuit comprising a plurality of bipolar transistors the emitters of which are connected to external terminals each.
Chen J. Z. et al. in xe2x80x9cDesign and Layout of a High ESD Performance NPN Structure for Submicron BICMOS/Bipolar Circuitsxe2x80x9d, 1966 IEEE International Reliability Physics Proceedings, U.S., New York, vol. SYMP. 34, 1996, pages 227 to 232, describe circuits for protection against electrostatic discharges in which the emitter of a protective transistor is connected to ground.
Corsi M. et al., xe2x80x9cESD Protection of BICMOS Integrated Circuits Which Need to Operate in the Harsh Environments of Automotive or Industrialxe2x80x9d, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Lake Buena Vista, Fla., USA, Sep. 28 to 30, 1993, pages 209 to 213, also reveal ESD protection circuits in which one or more bipolar transistors are connected between a connecting pad and ground.
It is the object of the present invention to make available an ESD protective transistor providing space-saving ESD protection for integrated circuits with high operating voltages.
This object is met by an ESD protective transistor comprising a heavily doped p-type base region which is arranged in a lightly doped p-well and which is provided with a first terminal. In the lightly doped p-well, there is provided furthermore a heavily doped n-type emitter region. A heavily doped n-type collector region is separated from the lightly doped p-well by a lightly doped n-type region and is provided with a second terminal. In the ESD protective transistor according to the invention, the heavily doped n-type emitter region is not shorted with the heavily doped base region via a common electrode and, furthermore, is of floating design.
As an alternative, the doping types of the respective regions may be reversed.
The present invention is based on the finding that an ESD protective transistor with increased holding voltage can be provided if the emitter region of the ESD protective transistor is not provided with an external terminal. The inventors have recognized that in case of the known ESD protective element illustrated in FIG. 5, after onset of the avalanche breakdown on the collector side, the pn base-emitter diode will be polarized in flow or forward direction due to the voltage drop arising across the p-well, since base region and emitter region are shorted via a common electrode. After onset of the avalanche breakdown on the collector side, the element thus snaps back to its specific holding voltage defined by the ratio between the current gain of the collector-side avalanche breakdown (avalanche multiplication) and the current gain due to the transistor effect. However, this holding voltage may be below the operating voltage of the integrated circuit to be protected, so that switching on of the protective transistor during regular operation cannot be excluded with certainty.
According to the invention, the heavily doped base region and the heavily doped emitter region of the ESD protective transistor now are no longer shorted via a common electrode. Thus, after onset of the collector-side avalanche breakdown, there is no longer a pure flow polarization of the base-emitter junction, as in case of the element illustrated in FIG. 5, but rather parts of the base-emitter junction are operated in reverse direction due to the potential between grounded base region and non-connected emitter region, so that the onset of the transistor effect commences only with the breakdown of the base-emitter diode. Due to this transistor effect, the ESD protective element according to the invention snaps back to a holding voltage that is higher, by the amount of the base/emitter breakdown voltage, than in case of an ESD protective transistor in which base and emitter are shorted by a common electrode.
In preferred embodiments of the ESD protective transistor according to the invention, the base region and the emitter region are arranged in the base well in spaced apart manner, so that the breakdown voltage of the base-emitter diode can be adjusted by way of the spacing therebetween. Furthermore, in preferred embodiments of the ESD protective transistor the breakdown voltage of the collector-side avalanche breakdown can be adjusted by adjusting the lateral distance between heavily doped collector region and lightly doped base well.
The present invention thus provides an ESD protective transistor having an increased holding voltage as compared to known ESD protective transistors, with this holding voltage in preferred embodiments of the present invention being adjustable in layout to voltages above a demanded supply voltage by way of the distance between base region and emitter region in the base well. The structure according to the invention thus is suitable as ESD protection for higher voltages, without the possibility of switching on during regular operation of the integrated circuit. This leads to a considerable decrease of the susceptibility to interference in case of fluctuations in supply voltage. The reduced requirement of area as compared with solution approaches so far contributes to significant cost reduction in addition.
Further developments of the invention are indicated in the dependent claims.